Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.702147
Title: Exploring memristive nano-scale memory and logic architectures
Author: Yang, Yuanfan
ISNI:       0000 0004 5994 9616
Awarding Body: University of Bristol
Current Institution: University of Bristol
Date of Award: 2016
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Abstract:
Resistive memory, also known as memristor, is an emerging potential successor to traditional CMOS charge based memories. Memristor, a two terminal non-volatile device, stores data as resistance value. Memristor has properties such as low power, high package density, and is widely used in memory system including read only memory and flash memory. However, some issues such as sneak path current limit the performance of memristor based crossbar memory. Memristors have also recently been proposed as a promising candidate for future logic and reconfigurable computing. To this end, this thesis presents different techniques for memristor based design of logic and memory. This thesis has three key contributions. This first is the Verilog-A based effective complementary resistive switch model for simulation and analysis. Our proposed model captures desired non-linear characteristics using voltage based state control in contrast to previously current based state control. We demonstrate that such state control has advantages for our proposed CRS model based crossbar arrays in terms of symmetric ON /OFF voltages and significantly reduces sneak path currents with high noise margin compared to traditional memristor based architectures. To validate the effectiveness of our Verilog-A based model, we carry out extensive simulations and analysis for different crossbar array architectures using traditional EDA tools. Based on the proposed CRS model, we propose a novel crossbar memory scheme using a configuration row of cells for assisting R/W operations. The proposed write scheme minimizes the overall power consumption compared to previously proposed write schemes and minimizes the state drift problem. We also propose two read schemes namely assisted-restoring and self-resetting read. In the assisted-restoring scheme, we use the configuration cells which are used in the write scheme, whereas we implement additional circuitry for the self-reset scheme to address the problem of the destructive read. Moreover, by formulating an analytical model of R/W operation, we compare various schemes. The overhead for the proposed assisted-restoring write/read scheme is an extra redundant row for the given crossbar array. For a typical array size of 200 x 200 the area overhead is about 0.5%. However, there is a 4X improvement in power consumption compared to the previously proposed write schemes. Quantitative analysis of the proposed scheme is presented by using simulation and analytical models. Secondly, we present a set of Complementary Resistive Switching (CRS) based stateful logic operations that use material implications to provide the basic logic functionalities needed to realize logic circuits. The proposed solution benefits from exponential reduction in sneak path current in crossbar implemented logic. We also present a closed form expression for sneak current and analyse the impact of device variation on the behaviour of the proposed logic blocks. Comparing with other techniques proposed in the literature, our technique requires several sequential steps to perform the computation. We validate the effectiveness of our solution through Cadence Spectre Circuit Simulator on a number of logic circuits. Also, we extend this approach for arithmetic circuits with an 8-bit adder and a 4-bit multiplier. Finally, we present a 2-transistor-memristor (2T2M) bit cell for ternary CAM (MTCAM) cell design, and novel full and partial match associative memories suitable for low-power applications. Our proposed circuit consists of memristors to store data and transistors as access devices, and utilizes complementary logic values at the input. The low power MTCAM splits the search lines to search logic 1 and logic 0 separately to reduce the search power consumption. For associative memories, the equivalent resistance of a search cell is a constant high value regardless of match patterns or mismatch patterns thus the search power is further reduced. Moreover, a current mirror structure is added in the partial match design to mitigate the impact of process variations improving the sense margin.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.702147  DOI: Not available
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