Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.700576
Title: Theoretical analyses and practical implementation of duobinary pulse position modulation using Mathcad, VHDL, FPGA and purpose-built transceiver
Author: Mostafa, Kamrunnasim
ISNI:       0000 0004 5993 9055
Awarding Body: University of Huddersfield
Current Institution: University of Huddersfield
Date of Award: 2015
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Abstract:
Duobinary pulse-position modulation (PPM), a novel channel coding scheme, has been proposed in this thesis as an alternative method of improving bandwidth utilisation efficiency and sensitivity over existing coding schemes such as digital PPM, dicode PPM, multiple PPM and offset PPM while operating over slightly or highly dispersive graded-index (GI) plastic optical fibre (POF) channels of limited bandwidth. Theoretical investigation based on simulations of mathematical models with maximum likelihood sequence detection (MLSD) at 1 Gbps on-off keying (OOK) data shows that duobinary PPM significantly outperforms optimised digital PPM at low fibre bandwidths by 8.7 dB while only operating at twice the original pulse code modulation (PCM) data rate. It has also been shown at high fibre bandwidth duobinary PPM gives a sensitivity of -42.2 dBm which is favourably comparable to digital PPM seven-level coding sensitivity of -44.1 dBm. Results presented in the thesis also demonstrate that at very low normalised fibre bandwidths (below 1 and down to 0.43) duobinary PPM outperforms dicode PPM by 1.2 dB requiring 27 x 103 photons per pulse compared to 40.3 x 103 required by Dicode PPM. Due to the use of MLSD at low bandwidths, wrong-slot errors are completely eliminated, and the effect of erasure and false-alarm errors are significantly reduced thus resulting in significantly improved sensitivity. Successful VHSIC hardware description language (VHDL) and field programmable gate array (FPGA) implementation of duobinary PPM coder, decoder and MLSD as a single system has been presented in the thesis. An FPGA embedded bit error rate (BER) test device has also been implemented for sensitivity measurements purposes and all the designs have been tested successfully with back-to-back testing. A purpose-built VCSEL 850 nm wavelength based transceiver system has been designed and successful functional tests have been carried out. Maximum operational data rate of the transceiver is currently 622 Mbps to match the maximum operating frequency of the FPGA, however, it has the capability to operate up to 3.2 Gbps. Further work on receiver characterisation and slot and frame synchronisation of duobinary PPM is required. All the results and analyses indicate that duobinary PPM is an ideal alternative to be considered for highly dispersive optical channels, and performance evaluation for higher bandwidths also favourably compares to existing coding schemes with only twice the expansion of original PCM data rate.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.700576  DOI: Not available
Keywords: T Technology (General) ; TA Engineering (General). Civil engineering (General)
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