Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.697372
Title: Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling
Author: Phatrapornnant, Teera
Awarding Body: University of Leicester
Current Institution: University of Leicester
Date of Award: 2007
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Abstract:
Following a review of previous work in this area, a presentation is made which illustrates the impact of a naive application of DVS in a system incorporating a time-triggered co-operative (TTC) scheduler. Novel algorithms (TTC-jDVS, TTC-jDVS2) and then introduced which more successfully integrate TTC and DVS techniques. These algorithms involve: (i) changes to system timer settings when the frequency is altered; (ii) use of a form of 'sandwich delay' to reduce the impact of changes to the scheduler overhead which arise as a result of frequency changes, and (iii) execution of jitter-sensitive tasks at a fixed operating frequency. The impact of these algorithms on both jitter and energy consumption is illustrated empirically on a representative hardware platform, using both 'dummy' task sets and a more realistic case study. In designs for which low jitter is an important consideration, at least a limited degree of task pre-emption may be required. A simple time-triggered hybrid (TTH) scheduler can be used to achieve such behaviour. A novel TTH secluding algorithm (TTH-jDVS) is presented and evaluated, again through use of dummy task sets and a case study. The third piece of experimental work presented in this thesis illustrates that --- in situations where minimal jitter is required --- hardware support is required. To illustrate the potential of such an approach a final case study is employed.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.697372  DOI: Not available
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