Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.679646
Title: Understanding, characterising and modelling the interactions between synthetic genetic circuits and their host chassis
Author: Algar, Rhys James Richmond
Awarding Body: Imperial College London
Current Institution: Imperial College London
Date of Award: 2013
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Abstract:
Characterisation and understanding of genetic components is a key part of both synthetic biology and systems biology. Quantitative knowledge of how DNA parts encode function allows parts to be predictably constructed into synthetic gene circuits. Less understood is how the expression of a synthetic gene circuit can have a detrimental effect on its host cell (the chassis) and how these effects can feed back to the behaviour of the circuit. In this thesis, we investigate how synthetic circuits use cellular resources (e.g. DNA polymerase, RNA polymerase, ribosomes, tRNA, etc.) to replicate and express and we quantify these effects and model gene expression in a way that accounts for this. This is done by considering this shared 'resource pool' as an interface between the host cell and the synthetic circuit. Through genetic engineering and synthetic biology, we have created a system that monitors the availability of shared resources in E. coli, thus enabling the quantification of the burden a synthetic circuit places on the cell's resources. We then measure the burden of a combinatorial library of different designs to examine how different genetic components influence the magnitude of burden. This is accompanied by a mathematical model. Through this method we work towards a system that will enable the prediction of how to optimise the design of a synthetic circuit with regards to its output and the levels of burden it places on a cell.
Supervisor: Ellis, Tom ; Stan, Guy-Bart Sponsor: Engineering and Physical Sciences Research Council
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.679646  DOI: Not available
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