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Title: Automated synthesis of delay-insensitive circuits
Author: Sayle, Roger Anthony
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1996
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The technological trend towards VLSI circuits built from increasing numbers of transistors continues to challenge the ingenuity of both designers and engineers. The use of asynchronous design techniques presents a method for taming the complexity of large concurrent VLSI system design and offers a number of attractive advantages over conventional design styles. In this thesis, we concentrate on the useful class of delay insensitive asynchronous circuits. These have the property that their correct operation is independent of the speed of the individual elements and the delays in the connecting wires. Traditionally, asynchronous circuits are considered much harder to design than their synchronous equivalents due to their inherent nondeterminism. The use of automated formal methods for generating such circuits shields the designer from this complexity. This allows the designer to abstract away from implementation issues and reason about the system behaviour in terms of concurrent processes or high level programs. Because each step of the compilation process can be shown to be sound, the resulting circuits are correct-by-construction. This thesis presents a compilation methodology for designing delay insensitive VLSI systems from behavioural specifications. The synthesis method makes use of a graph-based representation of the circuit's behaviour. Optimization of the global behaviour, by graph transformation, enables the generation of more efficient circuits than those produced by previous asynchronous circuit compilers based on syntax-directed translation. The resulting circuits are further improved by semantics-preserving circuit transformations. A compiler has been constructed that automatically performs the translation and transformation.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available