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Title: Characterisation of bipolar parasitic transistors for CMOS process control
Author: Wilson, David
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1992
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In integrated circuit manufacture, in particular, quality assurance, QA, is increasing rapidly in importance and in this research methods are developed and assessed which will assist with this. A review of current IC manufacturing is presented and CMOS technology shown to be dominant with BiCMOS seen to be a growth area. The role of Statistical Process Control, SPC, and the end for QA is also reviewed. This thesis addresses the problem and has defined some new techniques for the process control of a standard CMOS process. The approach is a novel one employing the concept of parasitic bipolar transistor test structures as a process control tool for present day CMOS circuits and, even more importantly, for BiCMOS devices. Test chip design and manufacture for the project are presented and the techniques proposed include: a) characterisation of parasitic JFETs to provide well depth information electrically b) the use of parasitic lateral bipolar transistors to estimate the sideways diffusion component associated with MOS transistors fabricated in a CMOS process c) the use of parasitic bipolar test structures to evaluate CMOS process uniformity. They provide useful parameters for processcontrol and, in some cases, have even been demonstrated to be more sensitive to CMOS process non-uniformities than those extracted from MOS devices themselves. Also process control information for today'sCMOS processes and an insight into the control of future BiCMOS processes.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available