Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.662285
Title: Design of an asynchronous processor
Author: Sotiriou, Christos Panagiotis
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2001
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Abstract:
This thesis investigates the implementation of asynchronous circuits and asynchronous computer architectures. In the area of asynchronous circuits, it proposes the direct-mapped approach to control circuit design, originally devised by Hollaar, mapped to CMOS technology. In the area of asynchronous computer architecture, it investigates scalable, concurrent computer architectures, with the aim of solving the problems of scaling performance and utilising the increasing device count. The design and implementation of two hardware structures, Shared Register Files and mnet (micronet) architectures is detailed, together with their incorporation into the design of an asynchonous prototype processor, the A1 chip. The Shared Register File approach provides a scalable and segmented datapath by partitioning the conventional monolithic register file into multiple register files which physically share registers. Communication and synchronisation between the shared register files takes place via the shared register. This approach can be used to implement a clustered uniprocessor or a single-chip multiprocessor system. The shared register file approach allows for the exploitation of program level concurrency, where different parts of the same program or different programs can run on the different shared register file datapaths. The design and implementation of shared register files is presented. The mnet approach is a methodology for asynchronous processor design, which allows fine-grain instruction level parallelism to be exploited. It implements a processor architecture as a non-linear pipeline with inputs at every pipeline stage. In this way, a mnet architecture exploits more fine-grain parallelism than a conventional pipelined architecture. The design and implementation of generic, scalable mnet architecture is described and evaluated.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.662285  DOI: Not available
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