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Title: A formal process for systolic array design using recurrences
Author: Puddicombe, Jonathan
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1992
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A systolic array is essentially a parallel processor which consists of a grid of locally-connected sub-processors which receive, process and pump out data synchronously in such a way that the patterns of data-flow to and from each processor is identical to the flow to and from the other processors. Such arrays are repetitive and modular and require little length of communication interconnection, so that they are relatively simple to design and are amenable to efficient VLSI implementation. The systolic architecture has been found suitable for implementing many of the algorithms used in the field of signal- and image-processing. A formal design method is a precisely defined method which, if followed, will yield a design satisfying a given specification. Such a method is amenable to proof that, if the method terminates, then the output design is valid. When proven correct, such methods are useful for designing equipment which is safety-critical or where a design fault discovered after manufacture would be expensive. This thesis presents a formal design method for implementing certain signal-processing and other algorithms as systolic arrays. As a necessary preliminary to the method, a calculus is defined. The basic concept, that of a 'computation', is powerful enough to express both abstract algorithms and those whose suboperations have been assigned a place and a time to execute. Computations may be composed or abstracted (by having variables hidden) or may have their variables renamed. The 'implementation' of one computation by another is defined. Using this calculus it is possible to formalise concepts like 'dependency' (of data or control) and 'system or recurrence equations', which often appear in the literature on systolic array design. The design method is then presented. It consists of four stages, pipelining of data dependencies, scheduling, pipelining of the control variables and allocation of subprocessors to the subcomputations.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available