Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.660469
Title: Self-timed field programmmable gate array architectures
Author: Payne, Robert
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1997
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Abstract:
Virtual hardware exploits the dynamic reconfigurability of Field Programmable Gate Arrays (FPGAs), but is currently limited by the delay properties of synchronous FPGA architectures. Synchronous circuits are difficult to manipulate dynamically, since this alters their internal delays. The speed-independent properties of self-timed circuits overcome this problem, thus allowing the full benefits of dynamic reconfiguration to be exploited. The general properties of self-timed systems, such as modularity, low-power and data-dependent delays also provide benefits to less dynamic FPGA systems as well. This thesis introduces a model for self-timed FPGA architectures called STACC (Self-timed Array of Configurable Cells). STACC architectures replace the global clock of an FPGA with an array of timing cells that provide local self-timed control to a region of logic blocks. STACC differs from previous self-timed FPGA architectures in that it does not disrupt the structure of the logic blocks. The STACC model is used to produced a self-timed version of the Xilinx XC6200. Example circuits for the self-timed XC6200 demonstrate the benefits of self-timing for implementing virtual hardware systems. Evaluation of the architecture shows that the implementation overhead of the timing array is reasonable, and that the self-timed XC6200 has the potential to out-perform the synchronous XC6200 through the use of data dependent delays.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.660469  DOI: Not available
Share: