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Title: Nanofabrication of silicon nanowires and nanoelectronic transistors
Author: Mirza, Muhammad M.
ISNI:       0000 0004 5348 0773
Awarding Body: University of Glasgow
Current Institution: University of Glasgow
Date of Award: 2015
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This project developed a robust and reliable process to pattern < 5 nm features in negative tone Hydrogen silsesquioxane (HSQ) resist using high resolution electron beam lithography and developed a low damage reactive ion etch (RIE) process to fabricate silicon nanowires on degenerately doped n-type silicon-on-insulator (SOI) substrates. A process to thermally grow high quality silicon dioxide (SiO2) (between 5-15 nm) is also developed to passivate onto the etched silicon nanowire devices to serve the purposes of gate dielectric and a diffusion barrier to minimize the donor deactivation. The measured interface state trap density (Dit) of the 10 nm thermally grown oxide is 1.3x10^10 cm^−2 eV^−1 with a breakdown voltage of ~7 V. Using optimized processes for lithography, dry etch and thermal oxidation, Hall bar and Greek cross devices are fabricated with mean widths from 45 to 4 nm on SOI substrates with a doping density ~ 2x10^19, 4x10^19, 8x10^19 and 2x10^20 atoms/cm^3 and electronically characterized at room and cryogenic temperatures (from 1.4 to 300 K) to allow resistivity, mobility and carrier density to be extracted directly as a function of temperature. This allowed to probe electron transport and scattering mechanisms in degenerately doped silicon nanowires. The mean free path is theoretically calculated and directly compared with the widths of the nanowires by which it can be approximated that the electron transport is 3 dimensional (3D) for the 12 nm wide nanowire which has likely to be changed to 2D and 1D for the 7 nm and 4 nm wide nanowires respectively. Moreover the experimental mobility is directly compared with a number of theoretically calculated mobilities using Matthiessen’s rule, where it has been determined that the neutral impurity scattering is the dominant scattering mechanism limiting the performance of silicon nanowires. Using silicon nanowires, junctionless transistors are fabricated on SOI substrate with a doping density ~ 4x10^19 atoms/cm^3 and electronically characterized at room and cryogenic temperatures (from 1.4 to 300 K). It was observed that reducing the width of channel from 24 to 8 nm, the transistor changed their operation from depletion to enhancement mode due to increase in the surface depletion at smaller length scales. Since the drain current in a junctionless transistor is proportional to the doping density, a high on-state drive current ~ 1.28 mA/µm has been observed with sub-threshold slope (SS) ~ 66 mV/decade at 300 K. Moreover temperature dependent measurements revealed a low SS ~ 39 mV/decade at 70 K and single electron oscillations at 1.4 K. Finally, independent arrays of 2 terminal nanowires devices with mean widths from 45 to 4 nm are fabricated on SOI substrate with a doping density ~ 8x10^19 atoms/cm^3 to detect polyoxometalate (POM) molecules [W18O54(SeO3)2]4−. A change in resistivity has been observed ~ 3.6 m ohm-cm (corresponds to ~ 13 % increase) when POM molecules are coated around the nanowires, shown n-type behaviour of molecules. POM molecules exhibit highly redox properties, therefore side-gated FETs with mean width ~ 4 nm were fabricated on SOI substrate with a doping density ~ 4x10^19 atoms/cm^3 where side-gate was used to apply alternative ± pulses of 20 V to charge and discharge the POM molecules to demonstrate flash memory operation. The average change in the threshold voltage was ~ 1.2 V between the charging (program) and the discharging (erase) cycles. The program/erase time is currently limited to 100 ms for a reasonable single-to-noise ratio. Moreover no significant decay in the stored charge has yet been measured over a period of 2 weeks (336 hours).
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: QC Physics