Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.653856
Title: Static dependency analysis of recursive structures for parallelisation
Author: Lewis, Tim
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2005
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Abstract:
A new approach is presented for the analysis of dependencies in complex recursive data structures with pointer linkages that can be determined statically, at compile time. The pointer linkages in a data structure are described by the programmer in the form of two-variable Finite State Automata (2FSA) which supplements the code that operates over the data structure. Some flexibility is possible in that the linkages can specify a number of possible target nodes for a pointer. An analysis method is described to extract data dependency information, also in the form of 2FSAs, from the recursive code that operates over these structures. For restricted, simple forms of recursion these data dependencies are exact; but, in general, heuristics are presented which provide approximate information. This method uses a novel technique that approximates the transitive closure of these 2FSA relations. In the context of dependency analysis, approximations must be ‘safe' in that they are permitted to overestimate dependencies thereby including spurious ones, but none must be missed. A test is developed that permits the safety of these approximate solutions to be validated. When a recursive program is partitioned into a number of separate threads by the programmer this dependency information can be used to synchronise the access to the recursive structure. This ensures that the threads execute correctly in parallel, enabling a multithreaded version of the code to be constructed. A multithreaded Micronet processor architecture was chosen as a target for this approach. Front- and back-ends of a compiler were developed to compile these multithreaded programs into executables for this architecture, which were then run on a simulation of the processor. The timing results for selected benchmarks are used to demonstrate that useful parallelism can be extracted.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.653856  DOI: Not available
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