Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.653631
Title: Gallium arsenide bit-serial integrated circuits
Author: Lam, S. C. K.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1990
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Abstract:
Bit-Serial architecture and Gallium Arsenide have essentially been mutually exclusive fields in the past. Digital Gallium Arsenide integrated circuits have increasingly adopted the conventional approach of bit-parallel structures that do not always suit the properties and problems of the technology. This thesis proposes an alternative by using a least significant bit first bit-serial architecture, and presents a group of 'cells' designed for signal processing applications. The main features of the cells include the extensive use of pseudo-dynamic latches for pipelining, modularity, and programmability. The logic circuits are mainly based on direct-coupled FET logic. They are also compatible with silicon ECL circuits. The target clock rates for these cells are 500MHz, at least ten times faster than previous silicon bit-serial circuits. The differences between GaAs and silicon technologies meant that the cells were designed from circuit level upwards. Further to these cells, a multi-level signaling scheme has been developed to substantially alleviate off-chip signaling. Synchonisation between signals are simplified, improving even further on the conventional bit-serial system, especially at the high bit-rates encountered in GaAs circuits. For on-chip signals, a single phase clock scheme has been developed for the GaAs cells, which maintains the low clock loading and high speed charactersitics of the pseudo-dynamic cells, while substantially simplifying clock distribution and generation. Two novel latch designs are proposed for this scheme. Test results available have already proved the concepts behind the two-phase clocking scheme, the latches, and the multi-level scheme. Further tests are taking place to establish their speed performance.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.653631  DOI: Not available
Share: