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Title: The limits of a decoupled out-of-order superscalar architecture
Author: Jones, Graham P.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1999
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This thesis presents a study into a technique for improving performance in out-of-order superscalar architectures. It identifies three technological trends limiting superscalar performance; they are the increasing cost of a main memory access, control dependencies and the greater hardware complexity of out-of-order execution. Decoupling is a technique that can provide higher performance through the machine of dynamically executing, asynchronous instruction streams. It offers the capability to improve ILP, through effective latency hiding and dynamic scheduling, and to reduce hardware complexity, through decentralised logic. This thesis evaluates this capability, by investigating the effectiveness of decoupled out-of-order superscalar architectures. This thesis identifies the degree to which operations can reorder (the degree of reordering) as the critical dimension to an out-of-order superscalar architecture. It investigates the effectiveness of decoupling by focusing on those design issues that determine the degree of reordering, and relaxes all other architectural constraints. This approach allows the thesis to establish the limitations of decoupled out-of-order superscalar architectures. The results from this thesis show that a decoupled architecture, through dynamically reordering small instruction windows provides a possible solution to the problem of latency hiding and issue logic complexity.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available