Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.652056
Title: Turbo decoder VLSI implementations for multi-standards wireless communication systems
Author: Han, Jong Hun
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2006
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Abstract:
This thesis presents high performance turbo decoder architecture for VLSI implementation in terms of area, power and critical path delay. A Max-Log-MAP (MLMAP) algorithm is used to implement the turbo decoder with sliding window (SW) method to reduce the latency. Low power and area efficient turbo decoder implementation is achieved by reducing memory blocks required to control the SW method and to store the branch metrics used for computing log-likelihood-ratio (LLR). Retiming and reordering method is applied to implementing the units needed to calculate the LLR and the state metrics, to save hardware costs. A novel method is proposed to achieve high speed turbo decoder implementation for high throughput without significant area and power overheads. The proposed method addresses the inherent critical path delay problem in the state metric computation process by normalising the branch metrics. A two-step soft-output Viterbi algorithm (TSOVA) based turbo decoder is implemented exploiting a novel concept for implementing a traceback algorithm (TBA) to achieve low area and power turbo decoder implementations as compared to the MLMAP turbo decoder without any significant BER performance degradation. Two reconfigurable application specific turbo decoders are implemented to support variable constraint length and binary and duo-binary turbo codes for targeting various wireless communication systems. The reconfigurable turbo decoder architectures are realised by a proposed mapping method applied to the process for computing the state metrics and the LLR values. It is found that radix-4 based turbo decoder architecture can be exploited to implement the reconfigurable turbo decoder for binary and duo-binary turbo codes.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.652056  DOI: Not available
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