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Title: Can deep-sub-micron device noise be used as the basis for probabilistic neural computation?
Author: Hamid, Nor Hisham
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2006
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This thesis explores the potential of probabilistic neural architectures as a computational paradigm for future nanoscale MOSFETs. The performance of the Continuous Restricted Boltzmann Machine (CRBM) implemented with simulated device noise in both Random Telegraph Signal (RTS) and “flicker”, or 1/f form is studied. A methodology for time domain RTS based noise analysis is described, based upon the known physics of future nanoscale MOSFETs. This noise is injected into a circuit implementation of the synaptic analogue multiplier and subsequently included in a behavioural model of a stochastic CRBM. The performance of the resultant “deep-sub-micron CRBM” compares well with that of the perfect Gaussian CRBM. Through simulation experiments, the CRBM with nanoscale MOSFET noise shows the ability to reconstruct training data with only minor performance degradation. These results do not prove that nanoscale MOSFET noise can be exploited in all contexts, and with all data, for probabilistic computation. The conclusion is, however, that nanoscale MOSFET noise is potentially usable in probabilistic neural computation. This thesis thus introduces a methodology for a form of technology-downstreaming and highlights the potential of probabilistic architecture for computation with future nanoscale MOSFETs.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available