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Title: Address generator synthesis
Author: Grant, Douglas M.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1991
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Increasing complexity of Application Specific Integrated Circuits (ASICs) has demanded a corresponding increase in the power of Computer Aided Design (CAD) tools, so that contemporary design tools can now synthesise an entire silicon architecture, given only a description of its functionality. Specialised automated synthesis techniques have now been applied to almost all parts of the architecture, but one area which remains unresolved is that of memory address generators. Previously combined with other logic synthesis techniques, less than optimal solutions were often found for generating memory address sequences, and this thesis examines address generator synthesis as an individual step in the design process, as part of an investigation into high level synthesis. The synthesis techniques developed for address generators in the AG1 and AG2 tools presented target specific architectural forms including counters, incrementors and ROM look-up tables, and the details of these are gathered within a comprehensive data structure which allows optimisation through hardware sharing to occur. At a slightly higher level, the specification of address sequences as a stage in memory synthesis is also investigated and a behavioural to register-transfer level silicon compiler, MC2 is presented. The data path and memory architectures constructed by this tool are used to produce realistic address generation requirements whose implementations are also presented, synthesised by AG2. It is shown that both array and non-array memory can benefit from more specialised address generator synthesis over the existing, mainly logic synthesis approach.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available