Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.651147
Title: Development and characterisation of a novel LDMOS macro-model for smart power applications
Author: Frere, Steven
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2005
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Abstract:
In the automotive industry, there is a strong trend that has increased the electronics in cars for various functions like fuel injection, electric control of doors and windows, electric chair adjustment, air-conditioning, drive-by-wire, brake-by-wire, etc. For these “automotive” systems, so-called smart power ICs must be used. These are chips in which the power functionality, e.g. the control of a motor is integrated with the logic control. There is also a trend towards operation at high voltages and integrating more intelligence using a microcontroller’s RAM.ROM memory and several sensors and interfaces. The final goal is the integration of a complete system on a single chip, a so-called power System-on-Chip (SoC). The interest in accurately modelling high-voltage transistors has increased in recent years due to the compatibility of these devices with standard CMOS technology. However, existing LDMOS models are not accurate enough for this task and SPICE models are especially weak when modelling AC performance. The limitation of these models lies in their lack of any capability to physically model some of the characteristic phenomena observed in LDMOS devices. The increased difficulty is related to complex 2D effects, specific to modern high voltage device architectures. This thesis presents a new physically based macro-model. This model is based on the investigations done on the key phenomena occurring in an LDMOS transistor. These phenomena were investigated by TCAD simulations and were confirmed by newly developed test-structures. The model is accurate for wide geometry and temperature variations as well for DC and AC operation. A novel corner extraction methodology based on neural networks has been developed making it possible to easily generate worst-case corners. The model was verified on device level as well on circuit level yielding good results.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.651147  DOI: Not available
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