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Title: 3D representation and characterisation of IC topography
Author: Elliott, Jane
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1998
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As IC feature sizes reduce and the use of multi-layer metal becomes more widespread, ICs are becoming increasingly topographically complex, and the effects of interconnect on circuit performance ever more significant. The electrical properties of interconnect must be accurately determined, and this can best be done by using 3D simulators which require an appropriate 3D representation of the circuit layout. The choice representation depends on the process used to manufacture the IC, which may include some reduction of topographical complexity using planarisation techniques. A test structure has been developed which can be used to electrically determine the degree of topographical planarity of an inter-metal dielectric. Simulated and experimental results obtained using this test structure are presented and shown to be comparable. Algorithms based on boolean polygon operations have been developed which produce 3D representations of integrated circuit layout directly from the mask data in a matter of minutes. These algorithms have been incorporated into software, 3DTOP, which has been used to automatically produce data for use with 3D capacitance simulators Raphael and FastCap, and with visualisation software POV-Ray. The results of 3D capacitance simulators of planar, semi-conformal and conformal representations of simple IC layouts created using 3DTOP have been compared. These indicate that the choice of 3D representation has a significant effect on simulated capacitance values, and that the importance of choosing the correct representation increases as interconnect track aspect ratios increase. Conventional and 3D extraction techniques have been used to determine the parasitic interconnect capacitances in a single transistor spatial light modulator circuit. The values extracted have been compared, and found to differ by up to 32%. The effect on circuit performance of the extracted capacitances has been shown to be significant.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available