Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.649777
Title: CMOS-compatible high-voltage transistors
Author: Duncan, Martin Russell
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1994
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Abstract:
Bipolar transistors are known to be the most suitable for high-voltage and power applications, due to their inherently greater current handling capability. In contrast, MOS technology is preferable for logic applications, due to its superior packing density. Therefore the 'ideal' solution to the smart power problem of integrating control elements on the same die as power switches is a marriage of the two different technologies. This results in a complex process that can only be cost effective in high volume applications. For ASIC applications and low volume product runs a less expensive compromise solution is needed. By analyzing both bipolar and MOS, low and high voltage devices, it was found that if more than one power transistor is needed on the circuit, and a single technology is to be used, then MOS power transistors are inherently easier to integrate into a low voltage process. In particular the lateral double-diffused transistor (LDMOS) with all terminal contacts on the surface is to be preferred. Analyzing a CMOS process, common processing steps were found for both the low and high-voltage devices, leading to a smart power solution that doesn't need many masking levels. By making small changes to an established n-well CMOS process, and developing a novel power transistor structure with a field oxidation separating the channel and drain, a 120 Volt n-channel power transistor could be realised within a conventional process with no additional processing steps. By adding one further masking layer, a complementary p-channel power transistor that supported -55 Volts could be fabricated. If these transistors were fabricated on a p- epitaxial layer on an n- substrate then by changing the p-channel power device structure, a breakdown voltage of -95 Volt could be achieved using only nine masking layers.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.649777  DOI: Not available
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