Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.649586
Title: ASIC implementations of the Viterbi Algorithm
Author: Dobson, Jonathan M.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1999
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Abstract:
The Viterbi Algorithm is a popular method for decoding convolutional codes, receiving signals in the presence of intersymbol-interference, and channel equalization. In 1981 the European Telecommunications Administration (CEPT) created the Groupe Special Mobile (GSM) Committee to devise a unified pan-European digital mobile telephone standard. The proposed GSM receiver structure brings together Viterbi decoding and equilization. This thesis presents three VLSI designs of the Viterbi Algorithm with specific attention paid to the use of such modules within a GSM receiver. The first design uses a technique known as redundant number systems to produce a high speed decoder. The second design uses complementary pass-transistor logic to produce a low-power channel equalizer. The third design is a low area serial equalizer. In describing the three designs, redundant number systems and complementary pass-transistor logic are examined. It is shown that while redundant number systems can offer significant speed advantages over twos complement binary, there are other representations that can perform equally well, if not better. It will also be shown that complementary pass-transistor logic can offer a small improvement for VLSI circuits in terms of power consumption.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.649586  DOI: Not available
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