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Title: GALS NoC
Author: Salisbury, Sean James
ISNI:       0000 0004 5363 172X
Awarding Body: University of Glasgow
Current Institution: University of Glasgow
Date of Award: 2015
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This portfolio thesis documents the work undertaken by the author for the Engineering Doctorate (EngD) programme. The research work completed for this thesis was undertaken at two sponsoring companies, Silistix and ARM. Demand for more complex yet power efficient devices has led to demand for System-on-Chip integrated circuit designs. To achieve this, ever increasing numbers of functional units in the form of Intellectual Property are being integrated into System-on-Chip designs. To cope with the increased design complexity challenge two key technologies are starting to be adopted. These are Globally Asynchronous Locally Synchronous to provide the ability to compose systems and Network-on-Chip to provide on-chip connectivity. This portfolio thesis considers some of the remaining difficulties in constructing Network-on-Chips in Globally Asynchronous Locally Synchronous designs. There are a number of major contributions presented in this thesis: the implementation of eleven orthogonal hazard defence circuit designs and techniques for Quasi-Delay Insensitive communication links; and the creation of a new Design-for-Test implementation and methodology enabling Quasi-Delay Insensitive Network-on-Chip components to achieve stuck-at test requirements in a commercial System-on-Chip design flow. Also presented is the creation of a test vehicle to enable analysis of synchronisation and serialisation within on-chip interconnects. The final contribution presented is a correctness and performance analysis of propagating memory barriers through on-chip interconnects to ensure correct system memory ordering and observation requirements.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (D.Eng.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available
Keywords: QA75 Electronic computers. Computer science ; TK Electrical engineering. Electronics Nuclear engineering