Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.642334
Title: Improving the flatness of microdisplay backplanes using chemical mechanical polishing
Author: Calton, David William
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2000
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Abstract:
Applications using liquid crystal on silicon (LCoS) spatial light modulators (SLM) demand a high level of device flatness. The overall backplane and individual mirror flatness directly influences SLM optical quality in a number of interrelated ways. They affect the liquid crystal (LC) cell gap uniformity, optical efficiency and LC alignment characteristics directly. In turn, the LC thickness variation and alignment quality affects device contrast ratio. The final cell gap uniformity, and LC alignment quality are also influenced by surface morphology, and by the chemistry of the surface over which the LC flows during cell filling. It is therefore critical to minimise the surface morphology and have a good understanding as to the LC's interaction with the surface over which it flows. Chemical mechanical polishing (CMP) can be used to increase device flatness and reduce the problems associated with surface morphology. A technique to remove the layout and process dependent surface topography using CMP has been investigated. Problems were initially encountered due to the presence of the large, feature dense, pixel array. These were overcome by the development of a novel pre-CMP dielectric etch step, resulting in a greatly improved post-CMP dielectric uniformity and a sub-nanometer RMS surface finish. Conventional planarisation techniques leave the mirrors standing proud of the surrounding dielectric surface. Two methods of reducing this mirror step-height have been compared, namely mirror damascene and via-damascene. The mirror-damascene method resulted in mirrors that are co-planar with the dielectric surface. While this improved the LC flow uniformity during cell filling, it introduced new concerns such as mirror dishing and array erosion. A more attractive technique is that of via damascene which produces vias that are level with the dielectric surface. This approach allows the deposition of thin high quality aluminium mirrors. Initial problems were encountered with via dishing and CMP induced dielectric degradation; both of which were addressed using a post-damascene dielectric buff.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.642334  DOI: Not available
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