Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.642175
Title: Standard CMOS floating gate memories for non-volatile parameterisation of pulse-stream VLSI radial basis function neural networks
Author: Buchan, L. William
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1997
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Abstract:
Analogue VLSI artificial neural networks (ANNs) offer a means of dealing with the non-linearities, cross-sensitivities, noise and interfacing requirements of analogue sensors (the problem of sensor fusion) whilst maintaining the compactness and low power of direct analogue operation. Radial Basis Function (RBF) networks, as a means of performing this function, have several advantages over other ANNs. The pulse-stream ANN technique developed at Edinburgh provides the additional benefit of implicit analogue-digital conversion and signal robustness. However, progressing this work requires the integration of high density analogue memory for parameterisation of the ANN since conventional weight refresh methods are too area and power hungry. For this purpose, standard CMOS floating gates have been proposed as these maintain the low process cost and energy availability of the neural circuitry. Investigation of this proposition proceeded in three stages: 1. Evaluation of the suitability of a standard process for the fabrication of floating gates and exposure of the issues involved: feasibility, analogue programmability, layout optimisation and modelling. 2. The interfacing of floating gates to Radial Basis Function (RBF) neural network circuits and development of programming approaches to cope with potentially destructive characteristics of high voltages and currents. 3. Development of circuits for programming floating gates using continuous-time feedback to facilitate a rapid weight downloading phase from a software model. Three chips were designed, fabricated and tested to explore each of these sets of issues. Detailed discussion and measurements are presented. Conclusions have been drawn about layout optimisation, programmability and device ageing and on the design and general suitability for purpose of standard CMOS floating gates. While these can be designed, interfaced to RBF circuits, and programmed to perform useful functions, their disadvantages make them more useful as a prototyping technique than as memory modules for inclusion in a final product.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.642175  DOI: Not available
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