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Title: An analogue VLSI study of temporally-asymmetric Hebbian learning
Author: Bofill Petit, Adria
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2005
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The primary aim of this thesis is to examine whether temporally asymmetric Hebbian learning is analogue VLSI can support temporal correlation learning and spike-synchrony processing. Novel circuits for synapses with spike-timing-dependent plasticity (STDP) are proposed. Results from several learning experiments conducted with a chip containing a small feed-forward network of neurons with STDP synapses are presented. The learning circuits proposed in this thesis can be used to implement weight-independent STDP and learning rules with weight-dependent potentiation. Test results show that the learning windows implemented are very similar to those found in biological neurons. The peaks of potentiation and depression, as well as the decay of both sides of the STDP learning window, can be tuned independently. Therefore, the circuits proposed can be used to explore learning rules with different characteristics. The main challenge for on-chip learning is the long term storage of analogue weights. Previous investigations of temporally asymmetric Hebbian learning rules have shown that weight-independent STDP creates bimodal weight distributions. This thesis investigates the suggestion that the bimodality of the learning rule may render the long-term storage of analogue values unnecessary.  Several experiments have been carried out to study the weight distribution created on-chop. With both weight-independent and moderate weight dependent learning rules the on-chip synapses develop either maximum or zero weights. The results presented show that, in agreement with theoretical analysis of STDP, the mean of the input weight vector decreases with the mean rate of the input spike trains. Some experiments reported indicated that the instability of weight-independent STDP could be used in some applications to maintain the binary weights learnt when the temporal correlations are removed from the inputs. Test results given show that both zero-delay correlations and narrow time windows of correlation can be detected with the hardware neurons. An on-chip two-layer network has been used to detect a hierarchical pattern of temporal correlations embedded in noisy spike trains. The analysis of the activity generated by the network shows that the bimodal weight distribution emerging from STDP learning amplifies the spike synchrony of the inputs.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available