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Title: Single event upset hardened embedded domain specific reconfigurable architecture
Author: Baloch, Sajid
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2007
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This thesis sets out to realize an embedded synthesisable domain specific reconfigurable core for DWT algorithms and investigates whether optimizing at both algorithmic and architecture level will yield a high performance hardware. A novel implementation scheme for the realization of a low power JPEG-2000 lifting based DWT is proposed and presented in this thesis. The scheme targets to reduce the switched capacitance by reducing the number of computational steps and data-path/arithmetic hardware through the manipulation of configurable logic blocks and interconnects. These resulted in a novel DWT specific reconfigurable architecture that is more efficient than a generic reconfigurable core. The thesis also investigates single event effects on the proposed reconfigurable core. The research resulted in a number of single event upset (SEU) mitigation schemes for the proposed core. The thesis introduces a novel approach to eradicate single event disruptions in sequential and configurable bit storage circuits. Two novel SEU mitigation schemes for combinational circuits are proposed through this thesis. These are based on partial triple modular redundancy and on dual hardware redundancy with comparisons. The proposed schemes are implemented n the proposed reconfigurable core and evaluated in terms of performance overheads and the results proved the efficacy of the proposed approaches over already in use mitigation schemes.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available