Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.641116
Title: Pulse-stream binary stochastic hardware for neural computation : the Helmholtz Machine
Author: Astaras, Alexander
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2004
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Abstract:
This thesis proposes a novel hardware implementation for a binary-state, probabilistic artificial neuron using the pulse-stream integrated circuit design methodology. The artificial neural network architecture targeted for implementation is the Helmholtz Machine, an auto-encoder trained by the unsupervised Wake-Sleep algorithm. A dual-layer network was implemented on the second of two prototype integrated circuit prototypes, intended for hardware-software comparative experiments in unsupervised probabilistic neural computation. Circuit modules have been designed to perform the synaptic multiplication and integration functions, the sigmoid activation function and to provide probabilistic output. All circuit design is modular and scaleable, with particular attention given to silicon area and power consumption. The neuron outputs the calculated probability as a mark-to-period modulated stream of pulses, which is then randomly sampled to determine the next state for the neuron. Implementation issues are discussed, such as a tendency for the probabilistic oscillators inside each neuron to phase-lock or become unstable at higher frequencies and how to overcome these issues through careful analogue circuit design and low-power operation. Results from parallel hardware-software experiments clearly show that learning takes place consistently on both networks, verifying that the proposed hardware is capable of unsupervised probabilistic neural computation. As expected due to its superior mathematical precision, the software-simulated network learns more efficiently when using the same training sets and learning parameters. The hardware implementation on the other hand has the advantage of speed, particularly when full advantage is taken of its parallel processing potential. The developed hardware can also accept pulse-width analogue neural states, a feature that can be exploited for the implementation of other existing and future auto-encoder artificial neural network architectures.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.641116  DOI: Not available
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