Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.640403
Title: Yield improvement of VLSI layout using local design rules
Author: Allan, Gerard A.
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 1992
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Abstract:
The demand for larger more complex systems on a single IC has shown a steady increase and to date has been met by improvements in fabrication technology. In the future it may not be possible to satisfy this demand in the same way, as it will become increasingly expensive to obtain the required process improvements. It seems likely that the demand for even larger single chip systems will continue and that the commercial success of these devices will become more heavily dependent on their yield. At the same time there is also a continuing trend towards more automated layout generation and these layouts are usually less dense than those produced using traditional hand-crafted designs. This thesis addresses the problem of maximising the yield of circuit layouts and introduces a yield improvement concept of Local Design Rules. These are integrated circuit layout rules that are used to increase a circuit's yield by making more efficient use of the circuit area. The rules define a more optimum feature size and spacing of components in relation to the surrounding layout geometry. This enables the 'unused' silicon to be reclaimed and used to enhance the circuit yield without violating the layout design rules. The type of circuit and nature of circuit layout to which local design rules can be applied to give useful yield improvement are discussed highlighting the problems in a fabrication process that can be improved by this type of layout manipulation. The impact of layout changes on the circuit performance that have been made on the suggestion of local design rules is addressed. Algorithms for the automatic application of track displacement, track width increase and contact increase local design rules are presented along with a spatial data structure suitable for efficient design rule checking of the suggested layout changes. These algorithms have been implemented and used to apply local design rules to integrated circuit layouts. Finally, several examples are presented with results from Monte Carlo yield simulations.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.640403  DOI: Not available
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