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Title: Domain specific high performance reconfigurable architecture for a communication platform
Author: Ahmed, Imran
Awarding Body: University of Edinburgh
Current Institution: University of Edinburgh
Date of Award: 2007
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Reconfiguration in an Integrated Circuit (IC) design has become increasingly important in the recent years. Some of the driving factors behind this trend are reduction in transistor size, ever changing standards, very high IC mask costs and short time to market. The programmable hardware design however suffers from performance degradation due to the added flexibility contrary to the end user demand for very high speed and low power electronics. Domain specific reconfigurable architectures provide a powerful solution to the problem by carefully tailoring the domain of the reconfiguration for the increased performance. This research work focused on investigating such low power reconfigurable VLSI architectures for forward error correction (FEC) to be deployed in a unified communication platform. The viterbi and turbo decoding are very well known techniques for FEC decoding and are essential components in many current and up coming standards such as WCDMA, WLAN, GSM, CDMA2000, ADSL and 3GPP. This thesis presents a reconfigurable unified implementation with a unified state machine control for combined turbo-viterbi decoder array. The amount of flexibility in the reconfigurable design is carefully tailored to meet the performance constraints imposed by these standards. Work on reconfigurable viterbi decoder provided the new novel reconfigurable trace back methodology, new segmentation and memory management techniques along with an open trellis structure that can support multiple standards. The work on reconfigurable turbo array generated novel implementation technique for low power input metrics management and reconfiguration, low power branch metrics generation, a new matrix normalization scheme and a completely flexible open trellis low power reconfigurable design. Turbo decoder design is combined with a novel low power implementation methodology for 3GPP internal interleaver. The interleaver implementation gives significant reduction in storage requirement for interleaved patterns and hence much improved power performance.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available