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Title: Scalable hierarchical networks-on-chip architecture for brain-inspired computing
Author: Carrillo, Snaider
Awarding Body: University of Ulster
Current Institution: Ulster University
Date of Award: 2013
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The brain is highly efficient in how it processes information and tolerates faults. Significant research is therefore focused on harnessing this efficiency and to build artificial neural systems that can emulate the key information processing principles of the brain. However, existing software approaches are too slow and cannot provide the dense interconnect for the billions of neurons and synapses that are required. Therefore, it is necessary to look to new custom hardware architectures to address this scalability issue and to enable the deployment of brain-like embedded systems processors. This thesis presents a novel Hierarchical Networks-on-Chip (H-NoC) architecture for SNN hardware, which aims to address the scalability issue by creating a modular array of clusters of neurons using a hierarchical structure of low and high-level routers. The proposed H-NoC architecture can be viewed as a flat 3D structure, which mimics to a degree the hierarchical organisation found in biological neural systems. Furthermore, this H-NoC architecture also incorporates a novel spike traffic compression technique to exploit SNN traffic patterns and locality between neurons, thus reducing traffic overhead and improving throughput on the network. In addition, novel adaptive routing capabilities between clusters, balance local and global traffic loads to sustain throughput under bursting activity. The thesis also reports on analytical results based on five large-scale scenarios, which demonstrate the scalability of the proposed H-NoC approach under varied traffic load intensities. Simulation and synthesis analysis using 65-nm CMOS technology demonstrate a good trade-off between high throughput and low cost area/power footprints per cluster. The thesis concludes with results on the mapping of the IRIS and Wisconsin Breast Cancer data sets using the proposed H-NoC architecture, and validates in FPGA hardware, the analytical performance. Most importantly, the FPGA implementation of both benchmarks demonstrates that the H-NoC architecture can provide up to 100x speedup when compared with biological real-time system equivalents.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available