Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.633518
Title: Hybrid-logarithmic arithmetic and applications
Author: Lee, Peter
Awarding Body: University of Kent
Current Institution: University of Kent
Date of Award: 2011
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Abstract:
This thesis is a contribution to the existing body of research on logarithmic arithmetic and signal processing. The implementation of log2 arithmetic circuits using modem digital hardware has been an area of active research for over 40 years. In this time over 400 academic papers in journals and conferences have been published and more than 40 patent applications submitted. At the time of writing there are at least 6 different research groups around the world actively working on new algorithms for conversion to and from the logarithmic domain and using logarithmic arithmetic and logarithmic signal processing in a wide range of academic, industrial, consumer and scientific applications. This thesis is separated into two sections. The first section deals with algorithms for logarithmic and anti-logarithmic conversion. It includes an overview and comparison of existing conversion algorithms before presenting two new conversion architectures which are more computationally efficient and suitable for implementation in both ASIC and VLSI technologies. The second section presents material published by the author on two specific applications of logarithmic signal processing where a Hybrid-Logarithmic Number System (Hybrid-LNS or Hybrid-Log) approach has been used. The first is the analysis, design· and implementation of a Discrete Cosine Transform (and its inverse) architecture which has been optimised for use in image compression applications such as JPEG and MPEG. The second describes the TOTEM neural network processor before discussing its implementation in both full-custom IC and FPGA technologies. The concentration. on Hybrid-LNS solutions indicates that this thesis does not discuss in any significant detail the problem of performing addition and subtraction in the logarithnlic domain. There has been extensive research into this problem in recent years and it · is beyond the scope of this thesis. This work is intended to add to the continued debate about the advantages/disadvantages of Hybrid-LNS architectures over "pure" logarithmic or LNS processors.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.633518  DOI: Not available
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