Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.628794
Title: Graphene FET circuit-level device modelling
Author: Umoh, Ime J.
ISNI:       0000 0004 5347 2909
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2014
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Abstract:
This thesis presents models for a graphene based field effect transistor (GFET). The graphene material has been widely studied since its synthesis in 2004 and the material holds promise for the next generation electronic applications. Therefore, there is a need to model its device characteristics. In this respect the contributions presented here are, firstly, a SPICE-compatible model for both dual gate and single gate graphene transistors. The derivation of the carrier transport of both hole and electron conduction results in a set of analytical equations. These derivations cover the three identified regions of operation as well as the boundary voltage conditions that define the regions. The Jacobian entries are shown to be continuous across the region boundaries. Secondly, circuit levels model of a single-layer GFET and multi layer GFET suitable for a direct implementation in SPICE. In this contribution, a more accurate threshold voltage compared to other models is derived. This contribution also shows how models can be extended to as many layers the graphene channelled transistor has. Finally, the introduction of a thermionic resistance, which is modelled in parallel with the resistance due to gate induced charges, provides a model for the temperature dependent channel resistance. The contribution goes further to derive equations between the off current and the vertical electric fields. Thus, giving a good estimation of the tunable bandgap opening in graphene. The models in this contributions are validated against experimentally measured transistor characteristics which have been carried out by other research groups and the models show a good agreement in all cases validated. The thesis equally presents the use of a floating gate to optimize the transistors characteristics. To illustrate these contributions, algorithms of the models have been implemented on the following CAD tools, HSPICE, VHDL-AMS and Berkeley SPICE. During the course of this work one journal and five conference papers have been published.
Supervisor: Kazmierski, Tomasz Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.628794  DOI: Not available
Keywords: TK Electrical engineering. Electronics Nuclear engineering
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