Use this URL to cite or link to this record in EThOS:
Title: Analogue to digital converter design in CMOS technology for low power applications
Author: Faiq, T.
Awarding Body: University College London (University of London)
Current Institution: University College London (University of London)
Date of Award: 2013
Availability of Full Text:
Access from EThOS:
Full text unavailable from EThOS. Please try the link below.
Access from Institution:
Miniaturization of integrated circuits (IC) has allowed very large scale integration (VLSI) of circuits. This has allowed personal communication devices to perform higher levels of data acquisition with faster speed. Due to robustness of digital systems most of the processing in ICs are digital. Therefore, the technology has been optimized for digital circuits. Still a small but very important part of these systems are analogue and it is very difficult to justify the modification of technology for analogue circuits. One of the most important analogue systems in these ICs are analogue to digital converters (ADC) which are implemented by switched capacitor (S/C) circuits. Fundamentally, the power consumption of S/C circuits increase as the power supply is reduced. Thus, reduced supply voltage tends to increase analogue circuit complexity and power consumption. This work focuses on development of digital calibration technique that allows the use of imprecise analogue circuits in order to reduce power consumption. The followings are achieved in the course of this research. An alternative background digital calibration technique that is based on deterministic error measurement. The technique can correct for capacitor mismatch and gain error due to insufficient op-amp DC gain. A system level simulation of the ADC have shown 15 dB signal-to-noise-plus-distortion-ratio (SNDR) and 31 dB spurious-free-dynamic-range (SFDR) improvement over a non-calibrated 12-bit ADC at 20 Ms/s. It also achieved an improvement of 4 LSB in INL and 0.6 LSB in DNL, respectively. A 12-bit 20 Ms/s 3.3 V pipeline ADC with the background digital calibration in 0.35 μm CMOS technology was designed and fabricated. However, primarily due to layout issues and to some extent due to equipment limitations the measured results showed only marginal improvement. A 10-bit 500 ks/s 5 V fully differential successive approximation ADC with a variable input range between 2-5 V in 0.35 μm CMOS technology with 1.5 mW power consumption designed and fabricated. This ADC can be used in moderate performance applications (resolution and speed), such as bio- impedance measurement.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available