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Title: Design and implementation of high-speed digital electronics hardware for telecommunications satellite on-board processors
Author: Walker, M.
Awarding Body: University College London (University of London)
Current Institution: University College London (University of London)
Date of Award: 2011
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Personal mobile voice and data communications have become ubiquitous in most developed areas of the modern world, with cellular mobile phone calls and text messages being perhaps the most common examples. Satellite operators provide comparable services that are not constrained by terrestrial cellular network coverage. With sustained demand for personal mobile communications via satellite and Moore’s law continuing to provide gains in integrated circuits, communications satellite vendors have the opportunity to supply new generations of equipment to fulfil this demand. Three linked projects are presented in chronological order, covering the design and implementation of high-speed digital electronics hardware for telecommunications satellite on-board digital signal processor equipments. Novel materials and hardware architectures are used to support the latest generations of integrated circuits thus enabling significant equipment performance increases, whilst meeting the strict resource budgets and constraints placed on satellite payload equipment. A novel processor equipment hardware architecture is described, which achieves high digital electronics power densities by using large aluminium nitride substrates to provide the physical component accommodation, electrical interconnections and thermal conduction path. The substrate material properties are studied and used to develop a baseline trace geometry and stack-up, optimised for routing capacity. The proposed architectures are then evaluated for feasibility. Alternative approaches are considered and a concept study of ‘thin PCB’ hardware undertaken. The development of the phase-2 next generation processor’s digital processor module is reported, from definition and design to testing, problem characterisation and resolution. After requirements capture and PCB stack-up design, the Clos network switch fabric routing is optimised for minimum PCB layer occupancy and signal integrity. The component pin-outs are optimised and ASIC and clock device packages designed, before the PCB is designed and fabricated. The module was tested at Engineering Model (EM) and Engineering Qualification Model (EQM) quality levels. Eight flight units will see deployment in the AlphaSat satellite, currently scheduled for launch in 2013. The research for this EngD took place under different phases of the Next Generation Processor (NGP) R&D programme, co-funded by Astrium and ESA. The work was carried out by the author, whilst in full time employment at the EADS Astrium Processor Products Group, in Stevenage, England. The group designs and delivers payload equipments, which use DSP algorithms, implemented in hardware, to realise flexible telecommunications satellite payloads, including the Inmarsat 4, Skynet 5 and AlphaSat processors.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available