Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.617806
Title: Performance optimisation of through silicon via integrated 3-D die stacks
Author: Grange, Matthew
Awarding Body: Lancaster University
Current Institution: Lancaster University
Date of Award: 2011
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Abstract:
This work describes a comprehensive modelling and analysis hierarchy which pursues the convergence point between system-level behaviour and low-level physical design of 3-D integrated circuits. The complete modelling, design and analysis methodology can be applied to wider technological design areas in deep submicron very large scale integrated systems such as massively parallel computational systems and high-speed digital signalling. The electrical parasitic signature of Through Silicon Vias (TSVs) are exhaustively defined with novel closed-form equations for various coupled and isolated 3-D interconnect configurations. The trade-offs in electrical performance for the 3- D interconnect for industry-standard on-chip CMOS signalling circuits including low-voltage, differential , current mode and shielding practices are then presented to define signalling conventions for 3-D circuits and arc compared to the planar 00- and off-chip interconnect. Thermal compact models of 3-D packages are discussed and used to develop a stand-alone thermal simulation tool to provide fast analysis of state-of-the-art IC packages. Moving from the physical-level, the communication infrastructure of 3-D ICs is rigorously investigated with particular attention to the packet-switching Network-on-Chip framework. The model for average distance is derived and rigorously analysed with cycle-accurate simulations to optimise the partitioning of multifunctional dies. The scalability and performance of 2-D and 3-D networks is then assessed where a custom cycle accurate simulator is developed for several traffic patterns, switch architectures and network configurations. Finally, to bring the physical and communication-level models into perspective, a set of hierarchical models are presented which are used to assess the computational efficiency of 2-D and 3-D silicon-based processors for early-chip planning. The development of comprehensive hierarchical models from the physical to the circuit to the system level in this work contributes significantly towards understanding the promises and limitations of future IC package design based on TSV integrated 3-D die stacking.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.617806  DOI: Not available
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