Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.616880
Title: Shared variable analyser for hardware descriptions
Author: Sharp, James
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 2013
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Abstract:
The application of hardware controllers within safety critical environments is becoming ever more common and complex. With increasing complexity" comes a higher potential for design errors. Hardware design tools such as Electronic Design Automation (EDA) tools, aim to expose these errors using equivalence checking l;Jetween abstract and concrete designs and apply functional property verification, driven by scenarios. Determining these scenarios using test environments, is however, not always straightforward. The EDA tools aid in determining the simulation coverage of test scenarios, but finding corner cases during testing to ensure complete coverage is difficult. Current research in hardware verification aims to find methods that can discover these extremes arid identify errors that reside within the design; one of these approaches employs formal methods. In this research, we determine that an existing Communicating Sequential Processes (CSP) compiler, the Shared Variable Analyser (SVA), is suitable as a basis for our work. SVA is designed for analysing threaded processes that interact with shared global variables. The systems analysed by this custom compiler reflect many of the behavioural concepts within the hardware design language, Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). A contribution of the thesis is the definition of formal approach for modelling hardware designs based on the concepts of shared signals. This approach is implemented by extending the SVA compiler; we call this augmentation of the compiler the Shared Variable Analyser for VHDL (SVA4VHDL). Another contribution of the thesis is the automatic generation from VHDL scripts to SVA4VHDL scripts, which are then provided as input to the compiler. This automatic generation ensures that scripts can be generated easily and repeatably without errors.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.616880  DOI: Not available
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