Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.606980
Title: Routes to cost effective realisation of high performance submicron gate InGaAs/InAlAs/InP pHEMT
Author: Ian, Ka Wa
Awarding Body: University of Manchester
Current Institution: University of Manchester
Date of Award: 2013
Availability of Full Text:
Access through EThOS:
Access through Institution:
Abstract:
The Square Kilometre Array (SKA) is known to be the most powerful radio telescope of its type. In support of its high observational power, it is estimated that thousands of antenna unit equipped with millions of LNA (low noise amplifier) will be deployed over a large area (radius>3000km). The stringent requirements for high performance and low cost LNA design bring about many challenges in terms of material growth, device fabrication and low noise circuit designs. For the past decade, the Manchester group has been wholeheartedly committed to the research and development of high performance, low cost Monolithic Microwave Integrated Circuit (MMIC) LNA with high breakdown (15V) and low noise characteristics (1.2dB to 1.5dB) for the SKA mid-frequency application (0.4GHz to 1.4GHz). The on-going optimisation of current design is hindered by the restriction of standard i-line 1µm gate lithography. The primary focus of this work is on the design and fabrication of new, submicron gate InGaAs/InAlAs/InP pHEMTs for high frequency applications and future SKA high frequency bands. The study starts with the design and fabrication of InGaAs-InAlAs pHEMT sub-100nm gate structure using E-Beam lithography. To address the problems of short channel effect and parasitic components, devices with 128nm T-gate structure, and with optimised device geometries and enhanced material growth, having fT of 162GHz and fmax of 183GHz are demonstrated, outlining the importance of device scaling for high speed operation. In addition, a gate-sinking technique using Pd/Ti/Au metallisation scheme was investigated to meet the requirement for single voltage supply in circuit design. Device with Pd-buried gate exhibits enhanced DC and RF characteristics and showed no degradation over 5 hours’ annealing at 230˚C. The implementation of this highly thermal stable Pd Schottky gate is key to improving the device’s long-term reliability at high-temperature operation. To solve the problem of low productivity in E-Beam lithography, a simple, low cost, technique termed soft reflow was introduced by utilising the principle of solvent vaporisation in a closed chamber. It provides a hybrid solution for the fabrication of submicron device using low cost i-line lithography. The integration of this new soft reflow process with the Pd-gate sinking technique has enabled the large-scale fabrication of 250nm T-gate pHEMTs, with excellent fT of 108GHz and a fmax of 119GHz and with device yields exceeding 80%. This novel soft reflow technique provides a high yield, fast throughput, solution for the fabrication of submicron gate pHEMT and other ultra-high frequency nanoscale devices.
Supervisor: Missous, Mohamed Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.606980  DOI: Not available
Keywords: pHEMT ; SKA ; III-V ; Pd ; InP ; InGaAs ; InAlAs ; Submicron ; T-gate ; Mushroom gate ; Reflow ; Solvent ; Economical ; Efficient ; 2DEG
Share: