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Title: On the static performance of lateral high voltage MOSFETs and novel nanoscale accumulation mode MOSFETs
Author: Iqbal, M. M.-H.
Awarding Body: University of Cambridge
Current Institution: University of Cambridge
Date of Award: 2009
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This research relates to static performance assessment of high voltage lateral MOSFETs and novel nanoscale accumulation mode MOSFETs. The static performance of the power semiconductor devices refers to breakdown voltage (BV) and specific on-resistance (sRon). Devising a relation or a power law between BV and sRon is absolutely crucial, as it determines the design criteria, the scaling of a technology with a voltage rating, the cost and ultimately the wider applicability of the technology in market. Here a technology-specific power law is proposed, which is applied to different Reduced SURface Field (RESURF) technologies for lateral power MOSFETs. The proposed power law introduces two technology-specific parameters, α and β, which are coupled with Baliga’s power law. Whilst in Baliga’s power law, parameters α and β are constant, here it will be demonstrated via comprehensive numerical simulations that parameters α and β can be different in various RESURF technologies. The numerical analysis also includes the variations of parameters α and β at maximum junction temperature of 125°C. First order 1D analytical models are proposed to examine the dependence of parameters α and β on technological process parameters and technology dictated material properties. A close match between the experimental data from the literature and the numerical-analytical results, establishes the validity of the newly proposed sRon vs. BV power law. This work takes into account that state-of-the-art RESURF technologies, i.e. single-, double-, triple-RESURF, partial SOI and linearly graded thin film SOI LDMOSFETs. The static performance of a nanoscale accumulation mode MOSFET incorporates to on-current, off-current, on-off ratio, threshold voltage, and subthreshold swing. A novel nanoscale transistor named Accumulation Metal Oxide Semiconductor Field Effect Transistor (AMOSFET) is proposed and experimentally demonstrated, which reveals excellent static performance. The AMOSFET is a very simple configuration that can have high performance transistors on thin films, a silicon-on-insulator (SOI) and nanowires (NWs). The configuration only requires a single doping type as the active layer, ohmic source and drain contacts spaced at minimum required distance from the gate, a minimum length gate, and a nanoscale dimension perpendicular to the gate. The nanoscale depth dimension forces the current path through an accumulated (on-state) or depleted (off-state) region. The numerical simulation study describes the static state operation, the role of gate capacitance and the importance of contacts’ ohmicity. Furthermore, the optimum device design considerations are also examined in numerical study. It is revealed in numerical study that the drain current has a weak dependence on the magnitude of the gate capacitance and the drive current is closely proportional to the mobility-doping density product.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available