Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.603374
Title: Complementary JFET logic in silicon carbide
Author: Habib, Hassan
Awarding Body: University of Newcastle Upon Tyne
Current Institution: University of Newcastle upon Tyne
Date of Award: 2013
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Abstract:
In the last decade or so, many prototype SiC devices and logic circuits have been demonstrated which have surpassed the performance of Si for the ability to function in extreme environments. The advance of silicon carbide technology has now reached a stage where commercialisation of high performance and energy efficient miniaturised devices and circuits is possible. These devices and circuits should be able to operate on the limited power resources available in harsh and hot hostile environments. These improvements require refining, experimenting and perhaps re-designing devices which can rightly claim their share in the current silicon dominant market. Consequently, there is a need for accurate simulation models for device engineers to understand device and circuit behaviour, examine performance trade-offs and verify the manufacturability of the design. This work includes the first comprehensive study, to the author’s knowledge, on the development and validation of 4H-SiC model parameters for high temperature, low power technology computer aided design (TCAD) finite element (FE) simulations. These model parameters are based on the physical and material properties of 4H-SiC and are derived from published data. The validation of these model parameters is performed using high temperature 4HSiC lateral junction field effect transistor (JFET) data, fabricated and characterised by our group at Newcastle University. TCAD tools and statistical techniques, such as design of experiment (DoE) and response surface modelling (RSM), play a key role in research to model and optimise semiconductor processes. These tools and statistical techniques also aid in studying the impact of process variability on device and circuit performance which ultimately affects the manufacturability and yield of the circuit. Based on TCAD tools and DoE and RSM statistical techniques, a iii systematic methodology is devised to optimise high temperature, four terminal SiC JFETs. Using calibrated FE simulation model, enhancement mode 4H-SiC (normally off) n- and p-JFETs are optimised for operation in extreme environments. The normally-off nature of these devices is desirable for logic devices in terms of reduced gate drive complexity and power dissipation. Unlike previously reported devices, the optimised SiC JFETs are designed such that not only the gate length is reduced to 2 μm (in contrast to the 10 μm reported elsewhere), but are also able to operate over a temperature range of −50 °C to 600 °C on a fixed voltage of 2 V, in contrast to the 20 V used in other work. Furthermore, the drain saturation current of the optimised JFETs increase with temperature which allows high on-to-off state current-ratio (Ion/Ioff) at elevated temperatures. High Ion/Ioff is essential for low power logic circuitry with fast switching. At 500 °C, Ion/Ioff ~ 103 for optimised (simulated) JFET as opposed to < 102 reported elsewhere. This is achieved by the choice of optimal gate bias, |Vg| = 2 V. The fourth, back-gate, terminal in the optimised JFET design provides an alternative route to tackle process variability. The effect of varying back-gate bias (Vsub) on the device performance parameters, such as threshold voltage (Vt), drain saturation current (Idss) and channel leakage current (Ioff) is also studied in detail. Using enhancement mode n- and p-JFETs, logic circuitry based on 4H-SiC complementary JFET (CJFET) technology is described for the first time, to the author’s knowledge. In order to assess the potential improvements in performance of digital logic functions as a result of using CJFET technology in their implementation, the static and dynamic characteristics of the most basic logic element, namely the inverter, are analysed using calibrated FE simulation model. The design and analysis of an inverter enables the design of more complex structures, such as NAND, NOR and XOR gates. These complex structures in turn form the building blocks for modules, such as adders, multipliers and microprocessors. The static and dynamic characteristics of CJFET logic inverters are analysed against operating frequency, temperature, supply voltage and fan-out. At 500 °C and operating at a supply voltage of 2 V, the inverter has noise margin high = 0.36 V, noise margin low = 0.57 V, undefined iv region = 0.51 V, propagation delay = 7ns, slew rate = 29.5 V/μs, maximum switching frequency = 10.6 MHz and static power = 353 nW. Apart from speed, these static and dynamic characteristics of the CJFET logic inverter, at 500 °C, are found to be comparable to those of silicon and strained silicon technology, at room temperature (RT). Currently, one of the biggest challenges faced by SiC technology in the development of complex ICs is high static power dissipation at 500 °C (~ 10−3 W). With the supply voltage scaled to 1 V, the static power of a CJFET inverter can further be reduced to 20.6 nW, but at an expense of degrading noise margin high to 0.15 V and noise margin low to 0.36 V. Finally, in CJFET logic arrays, random variations in manufacturing process parameters can cause significant variations in neighbouring gates or transistors and, therefore, can largely be accountable for poor yield. Using DoE and RSM based statistical approach, the effect of (±10%) process variability on CJFET logic inverter’s stability, in terms of noise margins, and efficiency, in terms of static power dissipation, are modelled and analysed at RT and 500 °C. It is found that the gate implant depth (tg) and channel doping (ND) have the most significant effect on the studied inverter responses. The fluctuation in these process parameters causes variations in threshold voltage (Vt) of the device which in turn affects the performance of the logic gate. However, these Vt variations can be tackled by the use of epitaxial gated devices which eliminate the issue of tg variations and by the adjustment of back-gate biasing (Vsub). Furthermore, with the continuing advances in SiC wafer quality, with minimum tolerances, it is inevitable that soon SiC CJFET technology can be integrated with SiC gas sensors for monitoring extreme environments.
Supervisor: Not available Sponsor: BAE Systems
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.603374  DOI: Not available
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