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Title: Rentian locality in chip multiprocessors
Author: Greenfield, D. L.
Awarding Body: University of Cambridge
Current Institution: University of Cambridge
Date of Award: 2010
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This thesis extends techniques from digital circuit interconnect prediction (in particular Rent’s rule) to analyse and predict interconnectedness in software, Chip-Multiprocessors (CMP) and Networks-on-Chip (NoC). In VLSI (Very Large Scale Integrated) circuits, the fractal connectivity of Rent’s rule is a well known predictor of the physical locality of interconnect across many orders of magnitude. It is shown how a generalised Rent’s rule can characterise and model both spatial and temporal locality in software, and it is demonstrated that locality effects can be exploited in Network-on-Chip design for fault tolerance. Evidence of Rentian fractal scaling in software is examined across several benchmarks using multiple methods. Given Rentian scaling, many fundamental results are derived for future many-core CMP architectures that relate number of cores, communication, on-chip memory and the Rent’s exponent, including some surprising scaling requirements towards fine-grain communication. It is also shown that existing models of an algorithm’s asymptotic time and energy cost are inadequate to account for physical communication costs and locality. A new analytical framework that utilises locality and its Rentian characterisation is demonstrated on several example algorithms, and a study is made of the ‘embedding problem’ for composing embeddings of algorithms together. Finally, in examining the interplay of communication and massively parallel computation at larger scales, we look at the mammalian brain as a proof-of-existence. We show that Rent’s rule also appears to apply to neuronal systems, and that this relates to the allometric scaling of communication to computation.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available