Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.587502
Title: Quasi-cyclic LDPC codes based on balanced incomplete block designs
Author: Wells, Andrew
Awarding Body: Lancaster University
Current Institution: Lancaster University
Date of Award: 2011
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Abstract:
The ever-increasing demand and requirements of communication systems necessitates research into advanced techniques to ensure reliable and optimum use of communication resources such as bandwidth. Channel characteristics such as noise, erasures and fading have a destructive effect on the transmission requiring novel approaches to obtain a reliable reconstruction at the receiver. In this thesis, we investigate error protection using linear block codes for Gaussian noise, erasure and fading channels. In the design of an error protection system, we focus on a class of near Shannon-limit approaching codes called Low-Density Parity-Check (LDPC) codes. The work presents and investigates a method of constructing LDPC codes using combinatorial mathematics known as Balanced Incomplete Block Designs (BIBD). Two classes of BIBDs are used to create new construction methods for generating quasi- cyclic (QC) LDPC matrices. The method of constructing QC-LDPC codes using BIBDs introduced offer flexible matrices while preserving the QC structure whilst ensuring efficient and low complexity encoding using linear shift registers. The structure provides similar performance to that of MacKay codes over the Gaussian channel, whilst also showing very good performance over both the random and burst erasure channels. The construction of QC-LDPC codes using BIBDs methods also result in codes with fast decoding convergence and low error floors. The introduced QC-BIBD-LDPC codes are applied to the power-line environment, which inhibits both frequency-selective fading and severe noise characteristics. The effects of the frequency-selective fading of the channel are reduced-using a Multi-carrier- Modulation (MCM) technique known as Orthogonal Frequency Division Multiplexing (OFDM). This MCM improves the operating performance of the system by effectively creating a flat fading environment. With the presence of impulsive noise present in power-line communications, this work introduces a combination of recursive filtering in conjunction with>tht QC-BIBD-LDPC coding to mitigate its effects. To implement the sum-product algorithm (SPA) for decoding Low-Density Parity-Check (LDPC) codes in a power-line communications channel impaired by highly impulsive noise, it is essential to find the right channel probability distribution to optimize the algorithm. However, the computational complexity of the reliability factor is very high. This research proposes the use of a Kalman filter to help cancel out the degradation effect of impulsive noise and consequently approximate the output of the filter as a normal random variable. It is shown that LDPC-coded OFDM system in conjunction with Kalman filtering offers an efficient alternative solution to compensate for the disturbances caused by impulsive noise. Simulation results are provided to demonstrate the performance with the Kalman filter; it is shown that a gain of 15dB is achievable over a system equipped with a channellimiter. The performance evaluation of error-control codes for research and development purposes using software implementation can be a timely and complex process due to computational complex algorithms. Simulating codes to very low BitIBlock error rates is a computationally intense operation, but it is shown that many aspects of simulating LDPC codes are perfect for parallel computation. The speed and accuracy of the QC-LDPC simulations can be greatly increased by utilising the parallel architecture of graphics processing units (GPUs) from conventional "central processing" using CPUs. It is shown that simulating the QC-BIBD-LDPC codes in chapter 3 using Graphics Processing Units simulation speed-ups are achievable when compared to equivalent implementations using central processing units (CPUs). These speedups are related to an increase in simulation complexity, with speedups increasing with an increase in block-size, number of Sum- Product Algorithm (SPA) iterations and number of codewords decoded in parallel.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.587502  DOI: Not available
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