Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.577252
Title: Parallel sparse matrix solution for direct circuit simulation on a multiple FPGA system
Author: Nechma, Tarek
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2012
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Abstract:
SPICE, from the University of California, at Berkeley, is the de facto world standard for circuit simulation. SPICE is used to model the behaviour of electronic circuits prior to manufacturing to decrease defects and hence reduce costs. However, accurate SPICE simulations of today's sub micron circuits can often take days or weeks on conventional processors. In a nutshell, a SPICE simulation is an iterative process that consists of two phases per iteration, namely, model evaluation followed by a matrix solution. The model evaluation phase has been found to be easily parallelisable unlike the subsequent phase, which involves the solution of highly sparse and asymmetric matrices. In this thesis, we present an FPGA implementation of a sparse matrix solver hardware,geared towards matrices that arise in SPICE circuit simulations. As such, we demonstrate how we extract parallelism at di�erent granularities to accelerate the solution process. Our approach combines static pivoting with symbolic analysis to compute an accurate task ow-graph which e�ciently exploits parallelism at multiple granularities and sustains high oating-point data rates. We also present a quantitative comparison between the performance of our hardware protrotype and state-of-the-art software package running on a general purpose PC equipped with a 2.67 GHz six-core 12 thread Intel Core Xeon X5650 microprocessor and 6 GB memory. We report average speedups of 9.65�, 11.83�, 17.21� against UMFPACK, KLU, and Kundert Sparse matrix packages respectively. We also detail our approach to adapt our sparse LU hardware prototype from a single-FPGA architecture to a multi-FPGA system to achieve higher acceleration ratios up to 38� for certain circuit matrices.
Supervisor: Zwolinski, Mark Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.577252  DOI: Not available
Keywords: QA75 Electronic computers. Computer science
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