Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.568262
Title: DSP electrical length calibration in satellite beamformers
Author: Akhtar, M. S.
Awarding Body: University College London (University of London)
Current Institution: University College London (University of London)
Date of Award: 2012
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Abstract:
This project has been constituted to exceed the sampling frequencies attained in the previous Astrium satellite communication signal processors (i.e. beamforming, null steering). Thus far these systems have been synchronous as the ADCs, DACs used, had comparatively low sample rate (i.e. less than or equal to 120 MHz) and were designed to have reset capability to resynchronise the system after power up, SEUs (single event upsets), radiation and other interference effects. Ever increasing demand for higher sampling rates requires a complex clocking scheme within the ADCs, DACs and DSPs, incorporating several frequency divider circuits, bringing with them the issues of uncertainties in the clock synchronisation. The clock ambiguities can be categorised into two types: the first type is SEU or power up related bit flip (i.e. change in flip-flop or register output polarity) and the second type is related to the thermal drift and the component aging. Obviously a bit flip in a clock divider circuit will cause a clock/data cycle discrepancy on the other hand the aging and thermal drift will cause a small amount of phase delay. In order to detect the discrepancies, two different methodologies are used namely: coarse calibration for the bit flip rectification and fine calibration for aging and thermal drift errors. Once a bit flip type error is detected it is handled by a phase commutator and a plesiochronous interface combination in the DPM (Digital Processor Module) while the thermal/aging type errors are very small in magnitude (i.e. <500ps) and are corrected by directly modifying the weighting co-efficient of the phase array antenna system. The project has been divided into 4 logical sections: the section 1 is dedicated to the firmware for calibration algorithms (Chapter 3 to Chapter 5) which detects and measures the electrical length anomalies due to the SEU and power up related uncertainties as well as the thermal and aging related phase errors. The section 2 consists of hardware design (Chapters 6 to Chapter 10 – DSP Breadboard) which is intended to be used for physical testing of the calibration algorithms developed in section 1. The operational firmware design (section 3- Chapter 11), deals with the telemetry read and program parameters upload, required on board the hardware developed in section 2 (DSP Breadboard). The section 4 is the DPM (Digital Processor Module) emulator (Chapter 12 and Chapter 13) which is developed to test all the calibration functions on the Alphasat Flight Program which has inherited all the firmware and hardware developed in sections 1 to 3. Finally the overall review of the project, including the associated hardware and firmware is presented in Chapter 14.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.568262  DOI: Not available
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