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Title: Low complexity capacity-approaching codes for data transmission
Author: Nelson, Christopher J.
Awarding Body: Lancaster University
Current Institution: Lancaster University
Date of Award: 2010
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This thesis analyzes the design of low complexity capacity approaching codes suitable for data transmission. The research documented in this thesis describes new and novel design methods for three well-known error control coding techniques, Turbo codes, LDPC block codes and LDPC convolutional codes, which are suitable for implementation in a number of modem digital communication systems. Firstly, we present Partial Unit Memory (PUM) based Turbo codes. A variant of Turbo codes which encompasses the advantages of both block and convolutional codes. The design methods of PUM Turbo codes are presented and Bit Error Rate (BER) simulations and Extrinsic Information Transfer (EXIT) chart analysis illustrates their performance. Partial Unit Memory codes are a class of low complexity, non-binary convolutional codes and have been shown to outperform equivalent convolutional codes. We present the EXIT charts of parallel concatenated PUM codes and PUM Woven Turbo Codes and analyse them to assess their performance compared with standard Turbo code designs. Resulting Extrinsic Information Transfer charts indicate that the proposed PUM-based codes have higher mutual information during iterative decoding than the equivalent Recursive, Systematic, Convolutional Turbo codes (RSC- TC) for the same Eb/No, i.e. the output of the decoders provides a better approximation of the decoded bits. The EXIT chart analysis is supported by BER plots, which confirms the behaviour predicted by the EXIT charts. We show that the concatenated PUM codes outperform the well-known turbo codes in the waterfall region, with comparable performance in the error floor region. In the second section we present Low Density Generator Matrix codes; a variant of LDPC codes that have low complexity encoding and decoding techniques. We present results of three construction methods and describe how LDGM codes can be modified to improve the error-floor region. We describe the design of random, structured and semi-random, semi- structured codes and how, by replacing the identity matrix with a staircase matrix, LDGM codes can show significant improvements in the error-floor region. Furthermore, we analyse the performance of serially concatenated LDGM codes and how they can benefit when we use the modified LDGM codes in either the outer code or the inner code. The results indicate that concatenated LDGM codes that incorporate LDGM staircase codes in the inner code will show improvements in error-floor performance while maintaining near capacity limit performances. While in the case of LDGM staircase codes being used as the outer codes no significant improvements in waterfall or error-floor regions are observed compared to a concatenated scheme that employs an LDGM identity outer code. Finally, we propose a new design of LDPC convolutional code, which we term as time invariant Low Density Parity Check Unit Memory (LDPC-UM) codes. The performance of LDPC block and Low Density Parity Check Unit Memory codes are compared, in each case, the Low Density Parity Check Unit Memory codes performance is at least as good as that of the LDPC block codes from which they are derived. LDPC-UM codes are the convolutional counterparts of LDPC block codes. Here, we describe techniques for the design of low complexity time invariant LDPC-UM codes by unwrapping the Tanner graph of algebraically constructed quasi-cyclic LDPC codes. The Tanner graph is then used to describe a pipelined message passing based iterative decoder for LDPC-UM codes and standard LDPC convolutional codes that outputs decoding results continuously.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available