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Title: Massively parallel softcore processors fo real-time FPGA-based MIMO detection
Author: Chu, Xuezheng
Awarding Body: Queen's University Belfast
Current Institution: Queen's University Belfast
Date of Award: 2012
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The requirements for higher computational capacity and lower cost of future high end real-time Digital Signal Processing (DSP) applications are rapidly growing. As a promising technique in wireless communication systems, Multiple-Input Multiple-Output (MIMO) enables significant high data rate wireless transmission, but on the other hand requires significant computing capacity from the underlying platform to enable real-time computing. Modern MIMO base stations use hundreds of DSP processors to enable this computing requirements, the solution however is still limited in computing capacity, and is high in power consumption, resource cost and size. In addition, high data rate services from MIMO detectors require high performance detection algorithms. Whilst significant progress has been made, the computational complexity of the algorithms is still very high. The thesis solves this problem from both embedded implementation and algorithm perspectives. In this thesis, a high performance and area efficient Field Programmable Gate Array (FPGA) based Processor Element (FPE) architecture has been presented. FPE is designed for FPGA-based DSP, enabling a powerful mix of software programmability and hardware configurability by constructing heterogeneous networks of softcore processors. To verify the performance and efficiency of FPE, a massively parallel softcore processor architecture has been constructed for Fixed-Complexity Sphere Decoder (FSD) MIMO, the resulting architecture enables real-time detection with hardware cost competitive to dedicated circuitry. It is the first software programmable architecture which supports the 480 Mbps throughput and 4 us latency of 802.11 n, with hardware cost competitive to dedicated circuit designs. I Through the exploration of hardware and software optimisation strategies of the processor, the computing capacity of FPGA can be efficiently exploited, and the resulting massively parallel softcore processor architecture for MIMO not only achieves the real-time throughput requirements of cutting edge wireless standards, but also enables 42% less equivalent hardware resources and 149\% increase in equivalent hardware efficiency compared to dedicated circuit design without redesigning the Hardware Description Language (HDL)/Register Transfer Level (RTL) hardware. This technique offers the potential to reduce the architecture design problem for DSP systems in general, and dynamic DSP design problems in particular, from a custom circuit design problem to a more tractable processor array configuration and programming problem, with no reduction in implementation efficiency or performance. In addition to high performance embedded architectures, two novel preprocessing algorithms for MIMO detection have been presented. State-of-the-art MIMO detector algorithms, such as FSD, rely on O(M_t"4) complexity of channel sequence preprocessing by Vertical-Bell Laboratories Layered Space-Time (V-BLAST). This high complexity preprocessing stage has not been recorded as real-time. By combining Sorted OR Decomposition (SORD) and Post Sorting Optimisation Algorithm (PSOA) with a particular FSD ordering scheme, this thesis describes a computationally efficient preprocessing solution for FSD. When compared to conventional MIMO preprocessing algorithms, SORD reduces the computational complexity of 4x4 to 7x7 MIMO cases by over 60-70%, suffering merely 0.16-0.26 dB performance reduction at the Bit Error Rate (BER) of 10"{-4}; in the cases where SORD fails to find optimal order, e.g., 8x8 to 16x16 MIMO cases, PSOA is applied after SORD to reduces the complexity by 28-55%, maintaining quasi Maximum Likelihood (quasi-ML) performance. The first real-time preprocessor architecture implemented by massively parallel softcore on FPGA also presents this saving.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available