Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.503118
Title: Hardware development based on a parallel programming language
Author: Coutinho, Jose Gabriel de Figueiredo
Awarding Body: Imperial College London (University of London)
Current Institution: Imperial College London
Date of Award: 2007
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Abstract:
The topic of this thesis is a novel hardware compilation approach called Haydn that combines the benefits of both behavioural and structural methodologies, so that it can support high-level synthesis, design exploration, design extensibility, and optional manual control. The main contributions of this thesis include the Haydn computation model, a parallel programming language called Haydn-C, a description of hardware design patterns based on the proposed approach, algorithms and techniques for automatic transformation, the implementation of a complete design-flow which performs source-level transformation, simulation and hardware synthesis, and finally the evaluation of the proposed language, algorithms and tools. The principal mnovation of the Haydn approach is to enable interleaving of manual design development with an automated scheduling procedure that supports user constraints. Designers can automatically restructure their designs to exploit different constraints, and to explore the best tradeoffs between size and speed. For this purpose, the Haydn C language includes an annotation facility to control the scheduling process. Pipelined and non-pipelined architectures can be generated with resources running at different speeds and with different latencies. To evaluate our approach, we include several case studies, such as Fibonacci number generation, RC2 encryption, posture analysis system, 3D free-form deformation, Gouraud shading, Montgomery multiplication and ID discrete cosine transform. For the 3D free-form deformation case-study, we derive an architecture running at 153MHz which is 328 times faster than software on a dual AMD MP2600+ processor machine running at 2.1GHz.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.503118  DOI: Not available
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