Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.494686
Title: Design fabrication of lateral silicon germanium heterojunction bipolar transistors
Author: Pengpad, Putapon
ISNI:       0000 0001 3482 9122
Awarding Body: University of Southampton
Current Institution: University of Southampton
Date of Award: 2008
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Abstract:
This work provides a detailed study of device structures and fabrication routes required for the realisation of lateral SiGe heterojunction bipolar transistors (HBTs). After a comprehensive study of BJT and HBT device technologies our own designs of lateral SiGe HBT are introduced. The first design investigated is a device proposed in earlier work that utilises "SOI cavities" and confined selective epitaxial growth. Process and device characteristic simulations were performed for devices of modest lithographic mode and thick SOI suggested the device would be reach typical SiGe Hbt performance levels with a cut off frequency (fT) of 15-22GHz, common emitter gain of 58-92 and maximum oscillation frequency (fmax) of 14GHz. The fabrication of the types of lateral HBT that been have explored require detailed understanding and control of selective epitaxial growth and etching techniques and each of these two important processes have been developed. Selective epitaxy growths on different crystallographic planes and seed window alignments have been carried out, and, as would be expected, selective epitaxial growth rate are seen to vary for each crystal plane. These different growth rates lead to different facet formations on lateral growth fronts that can inhibit lateral growth rates and thereby prevent the formation of suitable structures for HBT design. A mathematical model is developed that enables a prediction of these growth phenomena. The epitaxy and etching development studies have allowed us to propose a new design of lateral SiGe HBT, based on non-selective growth on SOI sidewalls. Simulations of this new design indicate high-speed performance with fT /fmax of 395/983GHz and 1.58ps ECL delay time on the 0.13mm lithographic node at collector currents of ~8mA and a common emitter gain around 600.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.494686  DOI: Not available
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