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Title: Ultrashallow junctions for strain-engineered NMOS devices
Author: Bennett, Nick
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 2008
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CMOS scaling is rapidly reaching physical limits, forcing the industry to consider alternative routes to realise performance improvements. Strain-engineering is one such option and is already widely exploited in order to improve charge transport in the device channel. Almost every leading chipmaker has announced their version of strain-engineered CMOS and strain is forecast to play a major role in future device generations.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID:  DOI: Not available