Low-power low-voltage analogue-to-digital converter design for mobile video and wireless applications
With the rapid embracing and deployment of Wideband Code Division Multiple Access (WCDMA)-based Third Generation (3G) mobile networks 1 in Europe and East Asia and with the ratification of the Digital Video Broadcast - Handheld (DVB-H) - terrestrial television for battery-powered mobile devices standard in Europe 2, minimization of hand-set power consumption is becoming a key requirement Higher baseband bandwidth is necessary for these enhanced wireless and mobile broadcast services, which translates to an increase in battery power utilization over existing second generation (2.xG) technology- enabled devices. The Analogue-to-Digital Converter (ADC) that does the transformation of received analogue baseband signals to the digital domain for digital demodulation and data extraction consumes some portion of the receiver front-end power budget and its rninirnization will contribute significantly to overall elongation of mobile device battery life. This research focuses on the design of power-efficient Nyquist and Over-sampled ADCs for DVB-H and GSM/WCDMA applications with the specific contributions to knowledge being the determination of optimal partitioning of pipeline ADCs for low power consumption, novel sampling switch linearization circuit for use in the design of high dynamic range Delta-Sigma (AS) ADCs and novel power and area efficient background calibration schemes for low-voltage high-speed 12-bit and higher resolution pipeline ADCs. A number of silicon devices were designed and fabricated (or in the process of fabrication) in the course of the research viz. A 10-bit 20.48 MS/s 1.5 V optimally partitioned pipeline ADC silicon in 0.35 microm CMOS technology for mobile DVB-H with measured results showing only 19 mW power consumption, 100 MHz Effective Resolution Bandwidth (ERBW), 56 dB Signal-to-Noise Ratio (SNR), 60 dB Spurious Free Dynamic Range (SFDR) and an ultra-low 0.19 pj/conversion energy consumption, one of the lowest reported for a measured device in the literature. A 13-bit 26 MS/s 135 kHz bandwidth, 2.7 V switched-capacitor AZ ADC silicon in 0.35 um BiCMOS technology for GSM frequencies with linearised sampling switch, achieving measured performance of 85.8 dB SFDR, 83.5 dB SNR and consuming 7 mW. An 11-bit 153.6 MS/s 1.92 MHz bandwidth, 2.7 V switched-capacitor AS ADC silicon in 0.35 um BiCMOS technology for WCDMA frequencies with linearised sampling switch, achieving measured performance of 76.9 dB SFDR, 72 dB SNR and consuming 14 mW. A 12-bit 120 MS/s 1.2 V pipeline ADC with novel digital background calibration in 0.12 um CMOS technology with over 85.5 dB simulated SFDR, 72.1 dB simulated SNR and consuming an estimated 100 mW.