Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.430376
Title: A self-reconfigurable system for software defined radio (SRS)
Author: Faust, Oliver
Awarding Body: University of Aberdeen
Current Institution: University of Aberdeen
Date of Award: 2005
Availability of Full Text:
Access through EThOS:
Full text unavailable from EThOS. Please try the link below.
Access through Institution:
Abstract:
This document introduces a Self-Reconfigurable system for Software defined radio (SR.S). The SRS is a modular processing platform which extends an ordinary PC system with Software Defined Radio capabilities. It consists of several daughter cards and one main board. The daughter cards connect the main board to external entities such as an analogue front end and the PC system. The main board hosts a single processor which executes signal processing algorithms and interfaces to external entities. The PC system controls which algorithms the processor executes and if necessary it initiates an algorithm change during runtime. The SRS system uses a reconfigurable architecture for the processor on the main board. This architecture provides a mechanism known as runtime reconfiguration to change the functionality or parts of the functionality of the processor. The PC system communicates with one part of the reconfigurable processor. This part reconfigures the signal processing part of the processor if the PC1 system initiates an algorithm change. I call this mechanism partial self-reconfiguration. Several components within the reconfigurable processor abstract the interfacing and signal processing tasks. The processor executes these components in parallel. I used a design methodology based on formal methods to design this component network. To be specific. I employed a model checker to validate a Communicating Sequential Processes (CSP) model of the component network. In a second step this CSP model was translated into hardware description code. The reconfigurable processor accelerates the baseband algorithms of digital communication standards. I studied the baseband algorithms which define the Orthogonal Frequency Division Multiplex (OFDM) modulation scheme. These algorithms have specific processing requirements. The specific-processor for the main board was selected based on the processing requirements of these algorithms. The SRS processing platform copes with the increasing algorithm complexity, higher demands for energy efficiency and flexibility. The modular system design provides a great deal of connection flexibility. This actually extends the idea of Software Defined Radio to wire or bus standards, i.e. software defines the bus standard. At the same time, formal methods ensure that the design, which defines the functionality of the reconfigurable processor, is reliable. Moreover, formal methods describe architecture and functionality of the system in a very compact manner. This provides the opportunity to document a hardware system completely. The OFDM algorithms provide a. deep insight into modern digital algorithms and how to accelerate these algorithms in a parallel architecture. This insight is necessary to draw up the specification for the system design.  The functionality of the reconfigurable processor was created with a design methodology based on formal methods. Compared with standard design methodologies the incorporation of formal methods speeds up the design process and the results are more reliable. The SRS system executes digital communication algorithms. Time and frequency synchronisation algorithms are amongst the most demanding, because they require realtime processing and they are very complex. The OFDM time and frequency synchronisation algorithms were improved with a technique called multi-rate signal processing. In a nutshell, multi-rate signal processing allows increased the time resolution and therefore it is possible to track a signal with finer steps.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.430376  DOI: Not available
Share: