Use this URL to cite or link to this record in EThOS: http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.425927
Title: Characterisation of source-gated transistors in amorphous silicon
Author: Balon, Frantisek
Awarding Body: University of Surrey
Current Institution: University of Surrey
Date of Award: 2005
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Abstract:
This thesis is concerned with new devices named Source-Gated Transistors (SGT) prepared in hydrogenated amorphous silicon. The aim of the thesis is to characterise SGT's having Schottky barrier sources in order to obtain a clear understanding of how they work, how they compare with a standard FET and their potential application. The construction and the principle of SGT operation differs from a conventional FET where the channel conductance is modulated by the gate voltage and current saturates when the drain region is depleted of charge. In comparison the current in the SGT is controlled by a reverse biased source barrier located opposite a gate electrode. Changing the gate potential affects the magnitude of the electric field at the source barrier and thereby the magnitude of the current flowing through the reverse biased barrier. Furthermore, saturation occurs when the semiconductor film is depleted by the reverse biased source barrier. The electrical characteristics of the SGT are very different from those of standard FET. In the first place the saturation voltage can be very much smaller and therefore the device can be operated in saturation at lower drain voltages giving less power dissipation. Secondly, the SGT is much less sensitive to the drain field than a FET which is manifested as a much better output impedance. Due to its specific device construction, the SGT can be operated with lower carrier concentrations, higher internal fields and reduced short channel effects enabling the possibility of devices at sub-micron or nanometres scale to be prepared with superior characteristics. SGT's prepared in amorphous silicon are much more stable than FET's for the same driving current. Also for the same device stability the SGT can operate at higher currents. Good agreement between experimental and simulated SGT transistor characteristics is presented allowing us to use Silvaco ATLAS modelling to obtain much deeper insight into SGT device physics. Where it was possible, experimental results are supported by modelling and vice versa. The influence of device geometry parameters such as source length, s-d separation, source barrier height, thickness of a-Si:H and SiN on the SGT properties is shown. It will be seen that these parameters are very closely linked together. These findings are used to improve transient and small signal response. The close link between the transient response and small signal response is presented and one can optimise the SGT device performance in both areas at once. In general the results show that stable, high performance electronics featuring SGT devices in amorphous silicon is a real possibility.
Supervisor: Not available Sponsor: Not available
Qualification Name: Thesis (Ph.D.) Qualification Level: Doctoral
EThOS ID: uk.bl.ethos.425927  DOI: Not available
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